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| IN74HC4051 ANALOG MULTIPLEXER DEMULTIPLEXER High-Performance Silicon-Gate CMOS The IN74HC4051 utilize silicon-gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF leakage currents. These analog multiplexers/demultiplexers control analog voltages that may vary across the complete power supply range (from VCC to VEE). The Channel-Select inputs determine which one of the Analog Inputs/Outputs is to be connected, by means of an analog switch, to the Common Output/Input.When the Enable pin is high, all analog switches are turned off. The Channel-Select and Enable inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. Fast Switching and Propagation Speeds Low Crosstalk Between Switches Diode Protection on All Inputs/Outputs Analog Power Supply Range (VCC-VEE)=2.0 to 12.0 V Digital (Control) Power Supply Range (VCC-GND)=2.0 to 6.0 V Low Noise * * * * * * ORDERING INFORMATION IN74HC4051N Plastic IN74HC4051DW SOIC TA = -55 to 125 C for all packages PIN ASSIGNMENT LOGIC DIAGRAM Single-Pole, 8-Position Plus Common Off FUNCTION TABLE Control Inputs Enable Select C B L L L L L L L L H L L H L H L L H L L H H L H H H X X ON Channels A L H L H L H L H X X0 X1 X2 X3 X4 X5 X6 X7 None PIN 16 =VCC PIN 7 = VEE PIN 8 = GND X = don't care 1 IN74HC4051 MAXIMUM RATINGS* Symbol Parameter VCC Positive DC Supply Voltage (Referenced to GND) (Referenced to VEE) VEE Negative DC Supply Voltage (Referenced to GND) VIS Analog Input Voltage VIN I PD Value -0.5 to +7.0 -0.5 to +14.0 -7.0 to +0.5 VEE - 0.5 to VCC+0.5 -1.5 to VCC +1.5 25 750 500 -65 to +150 260 Unit V V V Digital Input Voltage (Referenced to GND) V DC Input Current Into or Out of Any Pin mA Power Dissipation in Still Air, Plastic DIP+ mW SOIC Package+ Tstg Storage Temperature C TL Lead Temperature, 1 mm from Case for 10 C Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC Positive Supply Voltage (Referenced to GND) 2.0 6.0 V (Referenced to VEE) 2.0 12.0 VEE Negative DC Supply Voltage (Referenced to GND) - 6.0 GND V VIS Analog Input Voltage VEE VCC V VIN Digital Input Voltage (Referenced to GND) GND VCC V VIO* Static or Dynamic Voltage Across Switch 1.2 V TA Operating Temperature, All Package Types -55 +125 C ns 1000 0 t r, tf Input Rise and Fall Time (Channel VCC =2.0 V 500 0 Select or Enable Inputs) VCC =4.5 V 400 0 VCC =6.0 V For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may be drawn; i. e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range indicated in the Recommended Operating Conditions.. Unused digital input pins must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused Analog I/O pins may be left open or terminated. * 2 IN74HC4051 DC ELECTRICAL CHARACTERISTICS Digital Section (Voltages Referenced to GND) VEE=GND, Except Where Noted Symbol VIH Parameter Minimum High-Level Input Voltage, Channel-Select or Enable Inputs Maximum Low -Level Input Voltage, Channel-Select or Enable Inputs Maximum Input Leakage Current, Channel-Select or Enable Inputs Maximum Quiescent Supply Current (per Package) Test Conditions RON = Per Spec VCC Guaranteed Limit V 25 C to 85 125 -55C C C 2.0 1.5 1.5 1.5 4.5 3.15 3.15 3.15 6.0 4.2 4.2 4.2 2.0 4.5 6.0 6.0 0.3 0.9 1.2 0.1 0.3 0.9 1.2 1.0 0.3 0.9 1.2 1.0 Unit V VIL RON = Per Spec V IIN VIN=VCC or GND, VEE=-6.0 V Channel Select = VCC or GND Enable = VCC or GND VIS = VCC or GND VIO= 0 V VEE = GND VEE = - 6.0 A ICC A 6.0 6.0 2 8 20 80 40 160 DC ELECTRICAL CHARACTERISTICS Analog Section Symbol RON Parameter Maximum "ON" Resistance Test Conditions VIN=VIL or VIH VIS = VCC or VEE IS 2.0 mA(Figure 1) VIN=VIL or VIH VIS = VCC or VEE (Endpoints) IS 2.0 mA(Figure 1) VIN=VIL or VIH VIS = 1/2 (VCC- VEE) IS 2.0 mA VIN=VIL or VIH VIO= VCC- VEE Switch Off (Figure 2) VIN=VIL or VIH VIO = VCC- VEE Switch Off (Figure 3) VIN=VIL or VIH Switch to Switch = VCC- VEE (Figure 4) VCC V 4.5 4.5 6.0 4.5 4.5 6.0 4.5 4.5 6.0 6.0 6.0 6.0 VEE Guaranteed Limit V 25 C to 85 125 -55C C C 0.0 190 240 280 -4.5 120 150 170 -6.0 100 125 140 0.0 150 190 230 -4.5 100 125 140 -6.0 0.0 -4.5 -6.0 -6.0 -6.0 -6.0 80 30 12 10 0.1 0.2 0.2 100 35 15 12 0.5 2.0 2.0 115 40 18 14 1.0 4.0 4.0 A Unit RON IOFF ION Maximum Difference in "ON" Resistance Between Any Two Channels in the Same Package Maximum Off- Channel Leakage Current, Any One Channel Maximum Off- Channel Leakage Current, Common Channel Maximum On- Channel Leakage Current, Channel to Channel A 3 IN74HC4051 AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns) Guaranteed Limit VCC Symbol Parameter V 25 C 85C 125 to C -55C 550 465 370 tPLH, Maximum Propagation Delay, Channel- 2.0 110 93 74 tPHL Select to Analog Output (Figures 8 and 4.5 94 79 63 6.0 9) 90 75 60 tPLH, Maximum Propagation Delay , Analog 2.0 18 15 12 tPHL Input to Analog Output (Figures 10 and 4.5 15 13 10 6.0 11) 430 364 290 tPLZ, Maximum Propagation Delay , Enable to 2.0 86 73 58 tPHZ Analog Output (Figures 12 and 13) 4.5 73 62 49 6.0 515 435 345 tPZL, Maximum Propagation Delay , Enable to 2.0 103 87 69 tPZH Analog Output (Figures 12 and 13) 4.5 87 74 59 6.0 CIN Maximum Input Capacitance, Channel10 10 10 Select or Enable Inputs 35 35 35 CI/O Maximum Capacitance All Switches Analog Off I/O Common O/I 130 130 130 Feedthrough 1.0 1.0 1.0 Power Dissipation Capacitance (Per Package) (Figure 14) Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC Typical @25C,VCC=5.0 V, VEE=0 V 45 Unit ns ns ns ns pF pF CPD pF 4 IN74HC4051 ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0.0 V) Symbol Parameter BW Maximum OnChannel Bandwidth or Minimum Frequency Response (Figure 5) Off-Channel Feedthrough Isolation (Figure 6) Test Conditions fin=1 MHz Sine Wave Adjust fin Voltage to Obtain 0 dBm at VOS Increase fin Frequence Until dB Meter Reads -3 dB RL =50 , CL=10 pF fin= Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL =600 , CL=50 pF fin = 1.0 MHz, RL =50 , CL=10 pF Feedthrough Noise, Channel Select Input to Common O/I (Figure 7) VIN 1 Mhz Square Wave (tr = tf = 6 ns) Adjust RL at Setup so that IS= 0 A Enable = GND RL =600 , CL=50 pF RL =10 , CL=10 pF THD Total Harmonic Distortion (Figure 15) fin= 1 kHz, RL =10 k, CL=50 pF THD = THDMeasured - THDSource VIS =4.0 VPP sine wave VIS =8.0 VPP sine wave VIS =11.0 VPP sine wave VCC V 2.25 4.50 6.00 VEE V -2.25 -4.50 -6.00 Limit* 25 C Unit MHz 80 80 80 dB 2.25 4.50 6.00 2.25 4.50 6.00 -2.25 -4.50 -6.00 -2.25 -4.50 -6.00 -50 -50 -50 -40 -40 -40 mVP P 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 -2.25 -4.50 -6.00 -2.25 -4.50 -6.00 -2.25 -4.50 -6.00 25 105 135 35 145 190 % 0.10 0.08 0.05 * Limits not tested. Determined by design and verified by qualification. Figure 1. On Resistance Test Set-Up 5 IN74HC4051 Figure 2. Maximum Off Channel Leakage Current, Any One Channel, Test Set-UP Figure 3. Maximum Off Channel Leakage Current, Common Channel, Test Set-UP Figure 4. Maximum On Channel Leakage Current, Channel to Channel, Test Set-UP * Includes all probe and jig capacitance. Figure 5. Maximum On Channel Bandwidth, Test Set-UP * Includes all probe and jig capacitance. Figure 6. Off Channel Feedthrough Isolation, Test Set-UP * Includes all probe and jig capacitance. Figure 7.Feedthrough Noise, Channel Select to Common Out, Test Set-UP 6 IN74HC4051 Figure 8. Switching Weveforms * Includes all probe and jig capacitance. Figure 9. Test Set-UP, Channel Select to Analog Out Figure 10. Switching Weveforms * Includes all probe and jig capacitance. Figure 11. Test Set-UP, Analog In to Analog Out Figure 12. Switching Weveforms Figure 13. Test Set-UP, Enable to Analog Out 7 IN74HC4051 Figure 14. Power Dissipation Capacitance, Test Set-Up * Includes all probe and jig capacitance Figure 15. Total Harmonic Distortion, Test Set-UP EXPANDED LOGIC DIAGRAM 8 |
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